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 L6926
High efficiency monolithic synchronous step down regulator
General features

2V to 5.5V battery input range High efficiency: up to 95% Internal synchronous switch No external schottky required Extremely low quiescent current 1mA max shutdown supply current 800mA max output current Adjustable output voltage from 0.6V Low drop-out operation: up to 100% duty cycle Selectable low noise/low consumption mode at light load Power good signal 1% output voltage accuracy Current-mode control 600kHz switching frequency Externally synchronizable from 500kHz to 1.4MHz OVP Short circuit protection
MSOP8 VFSON8 (3x4.9x1mm) VFQFPN8 (3x3x1.0mm)
Description
The device is dc-dc monolithic regulator specifically designed to provide extremely high efficiency. L6926 supply voltage can be as low as 2V allowing its use in single Li-ion cell supplied applications. Output voltage can be selected by an external divider down to 0.6V. Duty Cycle can saturate to 100% allowing low drop-out operation. The device is based on a 600kHz fixed-frequency, current mode-architecture. Low Consumption Mode operation can be selected at light load conditions, allowing switching losses to be reduced. L6926 is externally synchronizable with a clock which makes it useful in noise-sensitive applications. Other features like Powergood, Overvoltage protection, Shortcircuit protection and Thermal Shutdown (150C) are also present.
Applications

Battery-powered equipments Portable instruments Cellular phones PDAs and hand held terminals DSC GPS
Application test circuit
L 6.8H VIN=2V to 5.5V C1 10F 6.3V SYNC VCC RUN 5 7 6 1 2 COMP
D01IN1305
VOUT=1.8V R2 200K C4 10F 6.3V
LX
R3 500K
8 PGOOD 4 C2 220pF 3 VFB GND R1 100K
October 2006
Rev 7
1/17
www.st.com 17
Contents
L6926
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.1 4.1.2 4.1.3 Low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 4.3 4.4
Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 5.2 5.3 5.4 5.5 DROPOUT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PGOOD (Power Good Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Adjustable output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OVP (Overvoltage Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 7 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
L6926
Pin settings
1
1.1
Pin settings
Pin connection
Figure 1. Pin connection (top view)
RUN COMP VFB GND 8 7 6 5 PGOOD SYNC VCC LX
1 2 3 4
D01IN1239AMOD
1.2
Pin description
Table 1. Pin description
Pin N 1 2 3 4 5 Name RUN COMP VFB GND LX Description Shutdown input. When connected to a low level (lower than 0.4V) the device stops working. When high (higher than 1.3V) the device is enabled. Error amplifier output. A compensation network has to be connected to this pin. Usually a 220pF capacitor is enough to guarantee the loop stability. Error amplifier inverting input. The output voltage can be adjusted from 0.6V up to the input voltage by connecting this pin to an external resistor divider. Ground. Switch output node. This pin is internally connected to the drain of the internal switches. Input voltage. The start up input voltage is 2.2V (typ) while the operating input voltage range is from 2V to 5.5V. An internal UVLO circuit realizes a 100mV (typ.) hysteresis. Operating mode selector input. When high (higher than 1.3V) the Low Consumption Mode is selected. When low (lower than 0.5V) the Low Noise Mode is selected. If connected with an appropriate external synchronization signal (from 500KHz up to 1.4MHz) the internal synchronization circuit is activated and the device works at the same switching frequency.
6
VCC
7
SYNC
8
Power good comparator output. It is an open drain output. A pull-up resistor should be connected between PGOOD and VOUT (or VCC depending on the PGOOD requirements). The pin is forced low when the output voltage is lower than 90% of the regulated output voltage and goes high when the output voltage is greater than 90% of the regulated output voltage. If not used the pin can be left floating.
3/17
Maximum ratings
L6926
2
2.1
Maximum ratings
Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol V6 V5 V1 V3 V2 V8 V7 Ptot TJ Tstg LX Pin Other pins Input voltage Output switching voltage Shutdown Feedback voltage Error amplifier output voltage PGOOD Synchronization mode selector Power dissipation at TA = 70 C Junction operating temperature range Storage temperature range Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002- "Human Body Model" Acceptance Criteria: "Normal Performance' Parameter Value -0.3 to 6 -1 to VCC -0.3 to VCC -0.3 to VCC -0.3 to VCC -0.3 to VCC -0.3 to VCC 0.45 -40 to 150 -65 to 150 1000 2000 Unit V V V V V V V W C C V V
2.2
Thermal data
Table 3. Thermal data
Symbol RthJA Parameter Maximum thermal resistance junction-ambient for MSOP8 Maximum thermal resistance junction-ambient for VFQFPN8 Value 180 56 Unit C/W C/W
4/17
L6926
Electrical characteristics
3
Electrical characteristics
Table 4. Electrical characteristcs (TJ = 25C, VIN = 3.6V unless otherwise specified) (1)
Symbol Vcc Vcc ON Vcc OFF Vcc hys Rp Parameter Operating input voltage Turn On threshold Turn Off threshold Hysteresis High side Ron Vcc = 3.6V, Ilx =100mA 100 240
(1)
Test condition After Turn on
(1)
Min 2
Typ
Max 5.5
Unit V V
2.2 2
V mV
300 m 400
215 Rn Low side Ron Vcc = 3.6V, Ilx =100mA
(1)
300 m 400
1 Peak current limit Ilim Valley current limit Vout fosc fsync Output voltage range Oscillator frequency Sync mode clock (2) Vcc = 3.6V
(1)
1.2
1.5 A 1.65
Vcc = 3.6V
(1)
0.85 1 0.9 Vfb 450 600 600 1.4
1.7 A 1.85 Vcc 700 KHz 800 1400 KHz V
(1)
400 500
DC characteristics Vsync = 0V, no load, VFB > 0.6V Vsync = 0V, no load, VFB > 0.6V Vsync = Vcc, no load, VFB > 0.6V RUN to GND, Vcc = 5.5V RUN to GND, VLX = 5.5V, Vcc = 5.5V RUN to GND, VLX = 0V, Vcc = 5.5V
(1)
200
300 A 300 A A A A
Quiescent current (low noise mode) Iq Quiescent current (low cunsumption mode) Ish Shutdown current
(1)
25 0.2 1
50
Ilx
LX leakage current
(2)
1
5/17
Electrical characteristics Table 4. Electrical characteristcs (continued) (TJ = 25C, VIN = 3.6V unless otherwise specified) (1)
Symbol Parameter Test condition Min Typ Max
L6926
Unit
Error amplifier characteristics 0.593 Vfb Ifb Run Vrun_H Vrun_L Irun RUN threshold high RUN threshold low RUN input current (2) 0.4 25 1.3 V V nA Voltage feedback Feedback input current (2) VFB = 0.6V
(1)
0.600 0.600 25
0.607 0.610
V V nA
0.590
SYNC/MODE function Vsync_H Vsync_L Sync mode threshold high Sync mode threshold low 0.5 1.3 V V
PGOOD section VPGOOD Power Good Threshold VOUT = Vfb VOUT = Vfb Run to GND VPGOOD = 3.6V 50 90 4 0.4 %Vout %Vout V nA
VPGOOD Power Good Hysteresis VPgood(low
)
Power Good Low Voltage Power Good Leakage Current (2)
ILKPGOOD
Protections HOVP Hard overvoltage threshold VOUT = Vfb 10 %Vout
1. Specification referred to TJ from -40C to +125C. Specification over the -40 to +125C TJ temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design
6/17
L6926
Operation description
4
Operation description
The main loop uses slope compensated PWM current mode architecture. Each cycle the high side MOSFET is turned on, triggered by the oscillator, so that the current flowing through it (the same as the inductor current) increases. When this current reaches the threshold (set by the output of the error amplifier E/A), the peak current limit comparator PEAK_CL turns off the high side MOSFET and turns on the low side one until the next clock cycle begins or the current flowing through it goes down to zero (ZERO CROSSING comparator). The peak inductor current required to trigger PEAK_CL depends on the slope compensation signal and on the output of the error amplifier. In particular, the error amplifier output depends on the VFB pin voltage. When the output current increases, the output capacitor is discharged and so the VFB pin decreases. This produces increase of the error amplifier output, so allowing a higher value for the peak inductor current. For the same reason, when due to a load transient the output current decreases, the error amplifier output goes low, so reducing the peak inductor current to meet the new load requirements. The slope compensation signal allows the loop stability also in high duty cycle conditions (see related section) Figure 2. Device block diagram
SY NC RUN V CC
OSCILLATOR LOW NOISE/ CONSU MPTION LOOP CONTR OL
G ND
SENSE PMOS
POW ER PMOS
CO MP
S LOPE G ND PEAK CL
FB V REF
0.6V
E/A
DRIV ER OV P
LX
PGOOD V REF
0.9V
ZERO CROSS ING G ND
V cc
SENSE NMOS
V cc
POW ER NMOS
PGOOD
V ALLEY CL
GND
7/17
Operation description
L6926
4.1
Modes of operation
Depending on the SYNC pin value the device can operate in low consumption or low noise mode. If the SYNC pin is high (higher than 1.3V) the low consumption mode is selected while the low noise mode is selected if the SYNC pin is low (lower than 0.5V).
4.1.1
Low consumption mode
In this mode of operation, at light load, the device operates discontinuously based on the COMP pin voltage, in order to keep the efficiency very high also in these conditions. While the device is not switching the load discharges the output capacitor and the output voltage goes down. When the feedback voltage goes lower than the internal reference, the COMP pin voltage increases and when an internal threshold is reached, the device starts to switch. In these conditions the peak current limit is set approximately in the range of 200mA400mA, depending on the slope compensation (see related section). Once the device starts to switch the output capacitor is recharged. The feedback pin increases and, when it reaches a value slightly higher than the reference voltage, the output of the error amplifier goes down until a clamp is activated. At this point, the device stops to switch. In this phase, most of the internal circuitries are off, so reducing the device consumption down to a typical value of 25A.
4.1.2
Low noise mode
If for noise reasons, the very low frequencies of the low consumption mode are undesirable, the low noise mode can be selected. In low noise mode, the efficiency is a little bit lower compared with the low consumption mode in very light load conditions but for medium-high load currents the efficiency values are very similar. Basically, the device switches with its internal free running frequency of 600KHz. Obviously, in very light load conditions, the device could skip some cycles in order to keep the output voltage in regulation.
4.1.3
Synchronization
The device can also be synchronized with an external signal from 500KHz up to 1.4MHz. In this case the low noise mode is automatically selected. The device will eventually skip some cycles in very light load conditions. The internal synchronization circuit is inhibited in shortcircuit and overvoltage conditions in order to keep the protections effective (see relative sections).
8/17
L6926
Operation description
4.2
Short circuit protection
During the device operation, the inductor current increases during the high side turn ON phase and decrease during the high side turn off phase based on the following equations: Equation 1
( V IN - V OUT ) I ON = ---------------------------------- T ON L
Equation 2
( V OUT ) I OFF = ------------------ T OFF L
In strong overcurrent or shortcircuit conditions the VOUT can be very close to zero. In this case ION increases and IOFF decreases. When the inductor peak current reaches the current limit, the high side mosfet turns off and so the TON is reduced down to the minimum value (250ns typ.) in order to reduce as much as possible ION. Anyway, if VOUT is low enough it can be that the inductor peak current further increases because during the TOFF the current decays very slowly. Due to this reason a second protection that fixes the maximum inductor valley current has been introduced. This protection doesn't allow the high side MOSFET to turn on if the current flowing through the inductor is higher that a specified threshold (valley current limit). Basically the TOFF is increased as much as required to bring the inductor current down to this threshold. So, the maximum peak current in worst case conditions will be: Equation 3
V IN I PEAK = I VALLEY + -------- T ON_MIN L
Where IPEAK is the valley current limit (1.4A typ.) and TON_MIN is the minimum TON of the high side MOSFET.
9/17
Operation description
L6926
4.3
Slope compensation
In current mode architectures, when the duty cycle of the application is higher than approximately 50%, a pulse-by-pulse instability (the so called sub harmonic oscillation) can occur. To allow loop stability also in these conditions a slope compensation is present. This is realized by reducing the current flowing through the inductor necessary to trigger the COMP comparator (with a fixed value for the COMP pin voltage). With a given duty cycle higher than 50%, the stability problem is particularly present with an higher input voltage (due to the increased current ripple across the inductor), so the slope compensation effect increases as the input voltage increases. From an application point of view, the final effect is that the peak current limit depends both on the duty cycle (if higher than approximately 40%) and on the input voltage.
4.4
Loop stability
Since the device is realized with a current mode architecture, the loop stability is usually not a big issue. For most of the application a 220pF connected between the COMP pin and ground is enough to guarantee the stability. In case very low ESR capacitors are used for the output filter, such as multilayer ceramic capacitors, the zero introduced by the capacitor itself can shift at very high frequency and the transient loop response could be affected. Adding a series resistor to the 220pF capacitor can solve this problem. The right value for the resistor (in the range of 50K) can be determined by checking the load transient response of the device. Basically, the output voltage has to be checked at the scope after the load steps required by the application. In case of stability problems, the output voltage could oscillates before to reach the regulated value after a load step.
10/17
L6926
Additional features and protections
5
5.1
Additional features and protections
DROPOUT operation
The Li-Ion battery voltage ranges from approximately 3V and 4.1V-4.2V (depending on the anode material). In case the regulated output voltage is from 2.5V and 3.3V, it can be that, close to the end of the battery life, the battery voltage goes down to the regulated one. In this case the device stops to switch, working at 100% of duty cycle, so minimizing the dropout voltage and the device losses.
5.2
PGOOD (Power Good Output)
A power good output signal is available. The VFB pin is internally connected to a comparator with a threshold set at 90% of the of reference voltage (0.6V). Since the output voltage is connected to the VFB pin by a resistor divider, when the output voltage goes lower than the regulated value, the VFB pin voltage goes lower than 90% of the internal reference value. The internal comparator is triggered and the PGOOD pin is pulled down. The pin is an open drain output and so, a pull up resistor should be connected to him. If the feature is not required, the pin can be left floating.
5.3
Adjustable output voltage
The output voltage can be adjusted by an external resistor divider from a minimum value of 0.6V up to the input voltage. The output voltage value is given by: Equation 4
R2 V OUT = 0.6 1 + ------ R
1
5.4
OVP (Overvoltage Protection)
The device has an internal overvoltage protection circuit to protect the load. If the voltage at the feedback pin goes higher than an internal threshold set 10% (typ) higher than the reference voltage, the low side power mosfet is turned on until the feedback voltage goes lower than the reference one. During the overvoltage circuit intervention, the zero crossing comparator is disabled so that the device is also able to sink current.
5.5
Thermal shutdown
The device has also a thermal shutdown protection activated when the junction temperature reaches 150C. In this case both the high side MOSFET and the low side one are turned off. Once the junction temperature goes back lower than 95C, the device restarts the normal operation.
11/17
Package mechanical data
L6926
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Figure 3.
DIM. MIN. A A1 A2 b c D (1) E 0.050 0.750 0.250 0.130 2.900 4.650 3.000 4.900 3.000 0.650 0.400 0.550 0.950 0 (min.) 6 (max.) 0.100 0.004 0.700 0.016 0.850 TYP. MAX. 1.10 0.150 0.950 0.400 0.230 3.100 5.150 3.100 0.002 0.03 0.010 0.005 0.114 0.183 0.114 0.118 0.193 0.118 0.026 0.022 0.037 0.028 0.033 MIN. TYP. MAX. 0.043 0.006 0.037 0.016 0.009 0.122 0.20 0.122
MSOP8 mechanical data & package dimensions
mm inch
OUTLINE AND MECHANICAL DATA
E1 (1) 2.900 e L L1 k aaa
Note: 1. D and F does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side.
MSOP8 (Body 3mm)
12/17
L6926 Figure 4.
Package mechanical data VFSON8 mechanical data & package dimensions
mm DIM. MIN. A A1 b D D2 E E2 e L ddd 0.45 0.25 2.85 2.20 4.75 3.00 0.30 3.00 2.30 4.90 3.10 0.65 0.65 0.05 0.0177 0.80 TYP. 0.85 MAX. 1.00 0.05 0.35 3.15 2.40 5.05 3.20 MIN. 0.031 TYP. 0.034 MAX. 0.039 0.0019 0.0098 0.012 0.0137 0.1122 0.118 0.1240 0.0866 0.0905 0.0944 0.1870 0.1929 0.1988 0.1181 0.1220 0.1259 0.0255 0.0255 0.0019 inch
OUTLINE AND MECHANICAL DATA
VFSON8 (3x4.9x1.0mm, Pitch 0.65)
Very thin Fine pitch Small Outline No lead
7575057 A
13/17
Package mechanical data Figure 5.
DIM. MIN. A A1 A2 A3 b D D2 E E2 e L ddd 0.30 1.49 2.23 0.18 0.80 TYP. 0.90 0.02 0.70 0.20 0.23 3.00 2.38 3.00 1.64 0.50 0.40 0.50 0.08 1.74 2.48 0.30 MAX. 1.00 0.05 MIN. TYP. MAX.
L6926
VFQFPN8 mechanical data & package dimensions
mm inch
OUTLINE AND MECHANICAL DATA
0.0315 0.0354 0.0394 0.0008 0.0020 0.0276 0.0079 0.0071 0.0091 0.0118 0.1181 0.0878 0.0937 0.0976 0.1181 0.0587 0.0646 0.0685 0.0197 0.0118 0.0157 0.0197 0.0031
VFQFPN8 (3x3x1.0 8mm)
Very thin Fine pitch Quad Packages No lead
7426334 B
14/17
L6926
Order codes
7
Order codes
Table 5. Order codes
Part number L6926 L6926013TR L6926D1 L6926D1013TR L6926Q1 L6926Q1TR Package MSOP8 MSOP8 VFSON8 VFSON8 VFQFPN8 VFQFPN8 Packaging Tube Tape and reel Tube Tape and reel Tube Tape and reel
15/17
Revision history
L6926
8
Revision history
Table 6. Revision history
Date Jan-2004 Sep-2004 Nov-2004 Sep-2005 Nov-2005 27-Oct-2006 Revision 2 3 4 5 6 7 First Issue in EDOCS dms. Changed the style look & feel. Add. new package VFSON8. Add. V8 and V7 parameter in the Table 2 - Absolute Maximum Ratings. Update Order Codes Updated "Table. 5 Electrical Characteristics". Added VFQFPN8 package and new part numbers. Added RthJA for VFQFPN8 in Table 3. Document has been reformatted. Changes
16/17
L6926
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17/17


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